IEEE

Asynchronous FIFO Design Based on Clock Gating Power Optimization

Abstract: Asynchronous First in First Out (FIFO) is critical for data buffering and clock domain crossing in modern digital systems, but their power consumption and reliability under metastability ...
IEEE

CNN-based receiver design for chirp-based asynchronous pulse code multiple access for massive IoT

Abstract: Asynchronous Pulse Code Multiple Access (APCMA) is a wireless access scheme for massive IoT that offers strong robustness to large-scale packet transmissions by encoding information in pulse ...
GitHub

Exploring the Agentic Frontier of Verilog Code Generation

This is a respository for exploring the Verilog code generation benchmark "Comprehensive Verilog Design Problems" (CVDP) with agentic modeling. This repository contains the code necessary to run CVDP ...
GitHub

Mod10_Asynchronous_Counter.v

JKFF ff0 (1'b1, 1'b1, clk, master_clr_n, count[0], q_not[0]); JKFF ff1 (1'b1, 1'b1, count[0], master_clr_n, count[1], q_not[1]); JKFF ff2 (1'b1, 1'b1, count[1 ...