Rated at 30 MIPS at a frequency of 40 MHz, the Field Programmable System Level Integration Circuit (FPSLIC) combines an 8-bit microcontroller with over 50 kgates of FPGA or PLD programmable logic.

Design tool firm Altium’s latest JTAG interface is intended to allow system developers to use the firm’s Nexar test tool with their existing FPGA development boards to interactively design and debug ...

To save system power, a low-power sleep mode can reduce the static supply current from about 10 mA to typically less than 100 µA. Therefore, MachXO devices should find homes in line-and battery ...

By Tam Do, Altera Corp. February 13, 2008 -- dspdesignline.com A digital communication system shares many similar building blocks that comprise a digital TV transmission system design. These key ...

Tool vendors Synplicity Inc. and Forte Design Systems Inc. bring system-level tools to PLD masses"Synplicity has been examining various C platforms for the last year and a half and decided to work ...

AICTE, Texas Instruments and NPTEL India have invited applications from undergraduate engineering students for a massive open online course (MOOC) on Embedded System Design using MSP430. The course ...

Xilinx continues to introduce FPGA development tools which it expects will make design of programmable devices accessible to a range of non-specialist developers. The SDSoC for the company’s Zynq All ...