EDN

HDL: A Design Flow Runs Through It

The modern hardware design flow is beginning to resemble America's great rivers. At one time they ran wild and free, but now they are constrained by an endless series of irrigation projects, dams and ...
Design-Reuse

ACTEL and HDL Works Announce Optimization of Graphical HDL Design Entry Environment for Actel Design Flow

Companies Also Announce Addition of HDL Works to Actel's EDA Alliance Program CAMBERLEY, UK and EDE, Netherlands, July 26 -- Actel Corporation (Nasdaq: ACTL) and HDL Works today announced the ...
Business Wire

Aldec’s Active-HDL Verification Capabilities Enhanced to Support SystemVerilog Constructs and UVM

HENDERSON, Nev.--(BUSINESS WIRE)--Aldec, Inc., a pioneer in mixed HDL language simulation and hardware-assisted verification for FPGA and ASIC designs, has greatly enhanced the verification ...
EDN

Four ways to build a CAD flow: In-house design to custom-EDA tool

An internal computer aided design (CAD) or design services engineer is responsible for delivering efficient, robust and high-quality design flow solutions. The design flow on a day-to-day basis keeps ...
Electronic Design

EDA Update: Mixed HDL/C-Language Design For FPGAs

Mixed HDL/C-Language design for FPGAs recently debuted, courtesy of Aldec Inc. and Celoxica Ltd. The Active-HDL+C integrated FPGA design environment combines Aldec's Active-HDL design entry and ...