Constrained random test pattern generation entered the scene a couple of decades ago as a better way to spend time and resources for the creation of stimulus. Stimulus definition had become an arduous ...

The huge undertaking of verifying a system-on-chip (SoC) design has challenged engineers for more than 20 years –– the amount of time spent on it hasn’t varied much from between 50-70% of the entire ...

Let’s say you have a block you need to verify. How do you know that the stimulus you are about to use is exhaustive enough and that you have covered the necessary scenarios/situations to prove it is ...

PARTNER CONTENT: Given the size and complexity of modern semiconductor designs, functional verification has become a dominant phase in the development cycle. Coverage lies at the very heart of this ...

Assertions have been key contributors in increasing confidence in the accuracy of the design & quality of verification since coding effective coverage is fundamental in ensuring the completeness of ...

Chip-verification teams often confront one fundamental question: “How well is the verification process exercising the design?” Attempts to answer this query have led to the development of several ...

If you don’t measure something you certainly can’t improve it in any meaningful way. This is especially important with a process that can never be completed due to the sheer magnitude of the ...