EDN

How to achieve 1 trillion floating-point operations-per-second in an FPGA

Based on recent technological developments, high-performance floating-point signal processing can, for the very first time, be easily achieved using FPGAs. To date, virtually all FPGA-based signal ...
Electronic Design

64-bit Floating Point Coprocessor Supports IEEE 754 Calculations

The uM-FPU64 floating point coprocessor chip provides support for IEEE 754-compatible, 64-bit floating point and integer calculations, expanded digital I/O, and analog input capabilities as well as ...
EDN

Tutorial: Floating-point arithmetic on FPGAs

[Editor's note: For an intro to fixed-point math, see Fixed-Point DSP and Algorithm Implementation. For a comparison of fixed- and floating-point hardware, see Fixed vs. floating point: a surprisingly ...
Design-Reuse

Single- and double-precision IEEE-754 floating-point unit

The GRFPU is an IEEE-754 compliant floating-point unit, supporting both single and double precision operands. The pipelined design combines high throu ...