Semiconductor Engineering

How Die Dimensions Challenge Assembly Processes

Multi-die assemblies are becoming more common and more complex due to technology advancements and market demands, but differing die dimensions are making this process increasingly challenging. To ...
Semiconductor Engineering

Challenges Grow For Creating Smaller Bumps For Flip Chips

New bump structures are being developed to enable higher interconnect densities in flip-chip packaging, but they are complex, expensive, and increasingly difficult to manufacture. For products with ...
EDN

ASE develops electroplated wafer bumping technology

TAIPEI, Taiwan — Advanced Semiconductor Engineering Inc., a supplier of packaging and testing services, has said that it has electroplated wafer bumping technology on 200-mm wafers and has begun a ...
EDN

Xilinx uses Unitive’s eutectic wafer-bumping process to lower FPGA costs

RESEARCH TRIANGLE PARK, N.C. — Flip-chip technology supplier Unitive Inc. here today announced qualification of its eutectic wafer-bumping process for volume production of high-density ...